SH7721 datasheet(54/1524 Pages) RENESAS

54 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page liv of lxii

Table 3.16

DSR Register Bits................................................................................................. 116

Table 3.17

DSP Operation Instruction Formats...................................................................... 118

Table 3.18

Correspondence between DSP Instruction Operands and Registers ..................... 119

Table 3.19

DC Bit Update Definitions ................................................................................... 120

Table 3.20

Examples of NOPX and NOPY Instruction Codes............................................... 122

Table 3.21

Variation of ALU Fixed-Point Operations............................................................ 126

Table 3.22

Correspondence between Operands and Registers ............................................... 126

Table 3.23

Variation of ALU Integer Operations ................................................................... 131

Table 3.24

Variation of ALU Logical Operations .................................................................. 133

Table 3.25

Variation of Fixed-Point Multiply Operation ....................................................... 135

Table 3.26

Correspondence between Operands and Registers ............................................... 136

Table 3.27

Variation of Shift Operations................................................................................ 137

Table 3.28

Operation Definition of PDMSB .......................................................................... 143

Table 3.29

Variation of PDMSB Operation............................................................................ 144

Table 3.30

Variation of Rounding Operation ......................................................................... 145

Table 3.31

Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 146

Table 3.32

Definition of Overflow Protection for Integer Arithmetic Operations.................. 146

Table 3.33

Variation of Local Data Move Operations............................................................ 147

Table 3.34

Correspondence between Operands and Registers ............................................... 148

Table 3.35

DSP Mode Extended System Control Instructions ............................................... 149

Table 3.36

Double Data Transfer Instruction ......................................................................... 151

Table 3.37

Single Data Transfer Instructions ......................................................................... 152

Table 3.38

Correspondence between DSP Data Transfer Operands and Registers ................ 153

Table 3.39

DSP Operation Instructions .................................................................................. 154

Table 3.40

Operation Code Map............................................................................................. 160

Section 4 Memory Management Unit (MMU)

Table 4.1

Access States Designated by D, C, and PR Bits ................................................... 183

Section 5 Cache

Table 5.1

Number of Entries and Size/Way in Each Cache Size.......................................... 197

Table 5.2

LRU and Way Replacement (when Cache Locking Mechanism is Disabled)...... 199

Table 5.3

Way Replacement when a PREF Instruction Misses the Cache ........................... 203

Table 5.4

Way Replacement when Instructions other than the PREF Instruction

Miss the Cache...................................................................................................... 203

Table 5.5

LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)................ 203

Table 5.6

LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)................ 204

Table 5.7

LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)................ 204

Table 5.8

Address Format Based on the Size of Cache to be Assigned to Memory............. 211

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