SH7721 datasheet(22/1524 Pages) RENESAS

22 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xxii of lxii

Section 21 Serial I/O with FIFO (SIOF) ............................................................. 679

21.1

Features.............................................................................................................................. 679

21.2

Input/Output Pins ...............................................................................................................681

21.3

Register Descriptions ......................................................................................................... 682

21.3.1 Mode Register (SIMDR) ...................................................................................... 683

21.3.2 Control Register (SICTR) ..................................................................................... 686

21.3.3 Transmit Data Register (SITDR) .......................................................................... 689

21.3.4 Receive Data Register (SIRDR) ........................................................................... 690

21.3.5 Transmit Control Data Register (SITCR) ............................................................. 691

21.3.6 Receive Control Data Register (SIRCR) .............................................................. 692

21.3.7 Status Register (SISTR)........................................................................................ 693

21.3.8 Interrupt Enable Register (SIIER) ........................................................................ 699

21.3.9 FIFO Control Register (SIFCTR) ......................................................................... 701

21.3.10 Clock Select Register (SISCR) ............................................................................. 703

21.3.11 Transmit Data Assign Register (SITDAR) ........................................................... 704

21.3.12 Receive Data Assign Register (SIRDAR) ............................................................ 706

21.3.13 Control Data Assign Register (SICDAR) ............................................................. 707

21.4

Operation ........................................................................................................................... 709

21.4.1 Serial Clocks......................................................................................................... 709

21.4.2 Serial Timing ........................................................................................................ 711

21.4.3 Transfer Data Format............................................................................................ 713

21.4.4 Register Allocation of Transfer Data .................................................................... 715

21.4.5 Control Data Interface .......................................................................................... 717

21.4.6 FIFO...................................................................................................................... 719

21.4.7 Transmit and Receive Procedures......................................................................... 721

21.4.8 Interrupts............................................................................................................... 727

21.4.9 Transmit and Receive Timing............................................................................... 729

21.5

Usage Notes ....................................................................................................................... 734

21.5.1 Regarding SYNC Signal High Width when Restarting Transmission

in Master Mode 2.................................................................................................. 734

Section 22 Analog Front End Interface (AFEIF) ................................................ 735

22.1

Features.............................................................................................................................. 735

22.2

Input/Output Pins ...............................................................................................................736

22.3

Register Configuration....................................................................................................... 736

22.3.1 AFEIF Control Register 1 and 2 (ACTR1, ACTR2) ............................................ 737

22.3.2 Make Ratio Count Register (MRCR) ................................................................... 740

22.3.3 Minimum Pause Count Register (MPCR) ............................................................ 740

22.3.4 AFEIF Status Register 1 and 2 (ASTR1, ASTR2)................................................ 740

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