SH7721 datasheet(13/1524 Pages) RENESAS

13 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xiii of lxii

4.3.2

TLB Indexing........................................................................................................ 179

4.3.3

TLB Address Comparison .................................................................................... 180

4.3.4

Page Management Information............................................................................. 182

4.4

MMU Functions................................................................................................................. 183

4.4.1

MMU Hardware Management .............................................................................. 183

4.4.2

MMU Software Management ............................................................................... 184

4.4.3

MMU Instruction (LDTLB).................................................................................. 184

4.4.4

Avoiding Synonym Problems ............................................................................... 186

4.5

MMU Exceptions............................................................................................................... 188

4.5.1

TLB Miss Exception ............................................................................................. 188

4.5.2

TLB Protection Violation Exception .................................................................... 189

4.5.3

TLB Invalid Exception ......................................................................................... 190

4.5.4

Initial Page Write Exception ................................................................................. 191

4.5.5

MMU Exception in Repeat Loop.......................................................................... 192

4.6

Memory-Mapped TLB....................................................................................................... 194

4.6.1

Address Array ....................................................................................................... 194

4.6.2

Data Array ............................................................................................................ 194

4.6.3

Usage Examples.................................................................................................... 196

4.7

Usage Note......................................................................................................................... 196

Section 5 Cache ...................................................................................................197

5.1

Features.............................................................................................................................. 197

5.1.1

Cache Structure..................................................................................................... 197

5.2

Register Descriptions ......................................................................................................... 199

5.2.1

Cache Control Register 1 (CCR1) ........................................................................ 200

5.2.2

Cache Control Register 2 (CCR2) ........................................................................ 201

5.2.3

Cache Control Register 3 (CCR3) ........................................................................ 204

5.3

Operation ........................................................................................................................... 205

5.3.1

Searching the Cache.............................................................................................. 205

5.3.2

Read Access.......................................................................................................... 207

5.3.3

Prefetch Operation ................................................................................................ 207

5.3.4

Write Access ......................................................................................................... 207

5.3.5

Write-Back Buffer ................................................................................................ 208

5.3.6

Coherency of Cache and External Memory .......................................................... 208

5.4

Memory-Mapped Cache .................................................................................................... 209

5.4.1

Address Array ....................................................................................................... 209

5.4.2

Data Array ............................................................................................................ 210

5.4.3

Usage Examples.................................................................................................... 212

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