SH7721 datasheet(55/1524 Pages) RENESAS

55 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page lv of lxii

Section 6 X/Y Memory

Table 6.1

X/Y Memory Virtual Addresses ........................................................................... 213

Table 6.2

MMU and Cache Settings..................................................................................... 216

Section 7 Exception Handling

Table 7.1

Exception Event Vectors....................................................................................... 225

Table 7.2

Instruction Positions and Restriction Types.......................................................... 235

Table 7.3

SPC Value When a Re-Execution Type Exception Occurs in Repeat Control

(SR.RC[11:0]

≥2)...................................................................................................237

Table 7.4

Exception Acceptance in the Repeat Loop ........................................................... 239

Table 7.5

Instruction Where a Specific Exception Occurs

When a Memory Access Exception Occurs in Repeat Control

(SR.RC[11:0]

≥1)...................................................................................................240

Section 8 Interrupt Controller (INTC)

Table 8.1

Pin Configuration.................................................................................................. 245

Table 8.2

Interrupt Sources and IPRA to IPRJ ..................................................................... 248

Table 8.3

Interrupt Exception Handling Sources and Priority (IRQ Mode) ......................... 270

Table 8.4

Interrupt Exception Handling Sources and Priority (IRL Mode).......................... 272

Table 8.5

Interrupt Level and INTEVT Code....................................................................... 275

Section 9 Bus State Controller (BSC)

Table 9.1

Pin Configuration.................................................................................................. 283

Table 9.2

Address Space Map 1 (CMNCR.MAP = 0).......................................................... 287

Table 9.3

Address Space Map 2 (CMNCR.MAP = 1).......................................................... 288

Table 9.4

Correspondence between External Pins (MD3 and MD4),

Memory Type of CS0, and Memory Bus Width................................................... 289

Table 9.5

Correspondence between External Pin (MD5) and Endians ................................. 289

Table 9.6

32-Bit External Device/Big Endian Access and Data Alignment......................... 331

Table 9.7

16-Bit External Device/Big Endian Access and Data Alignment......................... 332

Table 9.8

8-Bit External Device/Big Endian Access and Data Alignment........................... 333

Table 9.9

32-Bit External Device/Little Endian Access and Data Alignment ...................... 334

Table 9.10

16-Bit External Device/Little Endian Access and Data Alignment ...................... 335

Table 9.11

8-Bit External Device/Little Endian Access and Data Alignment ........................ 336

Table 9.12

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (1)-1..................................................................... 349

Table 9.12

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (1)-2..................................................................... 350

Table 9.13

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],

and Address Multiplex Output (2)-1..................................................................... 351

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