SH7721 datasheet(110/1524 Pages) RENESAS

110 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 48 of 1458

REJ09B0033-0300

2.3.4

Control Registers

The control registers (SR, SSR, SPC, GBR, and VBR) can be accessed by the LDC or STC

instruction in privileged mode. The GBR register can be accessed in the user mode.

The control registers are described below.

(1)

Status Register (SR)

The status register (SR) indicates the system status as shown below. The SR register can be

accessed only in privileged mode.

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

R/W

Processing Mode

Indicates the CPU processing mode.

0: User mode

1: Privileged mode

The MD bit is set to 1 in reset or exception handling

state.

R/W

The general registers R0 to R7 are banked registers.

0: In this case, R0_BANK0 to R7_BANK0 and R8 to

R15 are used as general registers.

R0_BANK1 to R7_BANK1 can be accessed by the

LDC or STR instruction.

1: In this case, R0_BANK1 to R7_BANK1 and R8 to

R15 are used as general registers.

R0_BANK0 to R7_BANK0 can be accessed by the

LDC or STR instruction.

The RB bit is set to 1 in reset or exception handling

state.

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