SH7721 datasheet(133/1524 Pages) RENESAS

133 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 71 of 1458

REJ09B0033-0300

Table 2.8

Logic Operation Instructions

Instruction

Instruction Code

Operation

Privileged

Mode

Cycles T Bit

AND

Rm,Rn

0010nnnnmmmm1001

Rn & Rm

→ Rn

–

AND

#imm,R0

11001001iiiiiiii

R0 & imm

→ R0

–

AND.B

#imm,@(R0,

GBR)

11001101iiiiiiii

(R0+GBR) & imm

→ (R0+GBR) –

–

NOT

Rm,Rn

0110nnnnmmmm0111

∼ Rm → Rn

–

Rm,Rn

0010nnnnmmmm1011

| Rm → Rn

–

#imm,R0

11001011iiiiiiii

| imm → R0

–

OR.B

#imm,@(R0,

GBR)

11001111iiiiiiii

(R0+GBR)

| imm → (R0+GBR)

–

TAS.B

@Rn

0100nnnn00011011

If (Rn) is 0, 1

→ T; 1 → MSB of

(Rn)

–

Test

result

TST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm; if the result is 0, 1

→ T–

Test

result

TST

#imm,R0

11001000iiiiiiii

R0 & imm; if the result is 0, 1

→

–

Test

result

TST.B

#imm,@(R0,

GBR)

11001100iiiiiiii

(R0 + GBR) & imm; if the result

is 0, 1

→ T

–

Test

result

XOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm

→ Rn

–

XOR

#imm,R0

11001010iiiiiiii

R0 ^ imm

→ R0

–

XOR.B

#imm,@(R0,

GBR)

11001110iiiiiiii

(R0+GBR) ^ imm

→ (R0+GBR)

–

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