32180 datasheet(21/839 Pages) RENESAS

21 / 839 page

1-4

OVERVIEW

32180 Group User’s Manual (Rev.1.0)

1.1 Outline of the 32180 Group

1.1.5 Built-in Clock Frequency Multiplier

• The 32180 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below.

XIN pin

(8MHz-10MHz)

BCLK (peripheral clock)

(16MHz-20MHz)

CPUCLK (CPU clock)

(64MHz-80MHz)

1/4

PLL

Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier

Table 1.1.2 Clock

Functional Block

Features

CPUCLK

• CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for

the M32R-FPU core, internal flash memory and internal RAM.

BCLK

• Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency

for the internal peripheral I/O and external data bus.

Clock output (BCLK pin output)

• A clock with the same frequency as f(BCLK) is output from this pin.

1.1.6 Powerful Peripheral Functions Built-in

(1) Multijunction timer (MJT)

(2) 10-channel DMAC

(3) Two 16-channel A-D converters (ADC)

(4) 6-channel high-speed serial I/O (SIO)

(5) Real-time debugger (RTD)

(6) 8-level interrupt controller (ICU)

(7) Three operation modes

(8) Wait controller

(9) 2-channel Full-CAN

(10) M32R family’s common debug function (Scalable Debug Interface or SDI)

32180 Datasheet(PDF) 21 Page - Renesas Technology Corp