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7733 Datasheet(PDF) 358 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 358 Page - Renesas Technology Corp |
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358 / 940 page  RESET 7733 Group User’s Manual 13–7 Timer B2 register 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 4B16 4C16 4D16 4E16 4F16 4A16 Address Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Processor mode register 0 One-shot start flag Timer A0 register Up-down flag Timer A1 register Register name Count start flag Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Access characteristics WO RW b7 b0 RW RW RW RW RW RW RW WO RW State immediately after reset 0016 0016 0016 0016 ? 0016 b7 b0 0016 00 0 00 0 00 0 0 0 0 WO RW RW RW Timer A0 mode register Timer A4 mode register RW RW RW 00 0 0 0 0 0 0 00 0 0 0 0 00 0 0 0 00 0 0 0 0 0 RW RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 Processor mode register 10 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V2 V2 V2 V3 V3 V1 Access characteristics at addresses 4616 to 5516 vary according to the timer’s operating mode. (Refer to chapters “6. TIMER A” and “7. TIMER B.”) V2 Access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B’s operating mode. (Refer to chapter “7. TIMER B.”) V3 Access characteristics for bit 1 at address 5E16 and its state immediately after reset vary according to the voltage level applied to pin CNVSS. (Refer to section “2.5 Processor modes.”) 13.1 Hardware reset Fig. 13.1.5 State of SFR area and internal RAM area immediately after reset (3) |
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