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7733 Datasheet(PDF) 359 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 359 Page - Renesas Technology Corp |
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359 / 940 page  RESET 7733 Group User’s Manual 13–8 0 RO UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 6B16 6C16 6D16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW(V2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset ? ? ? ? ? 0 00 0 ? 0 ? (V1) b7 b0 ? 0 0 0 0 0 00 0 0 0 0 0 00 0 00 0 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 00 0 0 0 1 00 0 0 00 0 0 0 00 0 0 00 0 0 00 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 00 0 0 0 0 0 0 00 0 0 00 0 0 00 0 ? ? ? 0 0 0 00 0 00 0 00 0 Value “FFF16” is set to the watchdog timer. (Refer to chapter “10. WATCHDOG TIMER.”) For access characteristics at address 6C 16, also refer to Figure 14.3.2. State immediately after reset for bit 3 at address 6F 16 vary according to the microcomputer. (Refer to Figure 14.3.3.) Do not write data to address 6216. sInternal RAM area (M37733MHBXXXFP: addresses 80 16 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset . When the stop or wait mode is terminated (when hardware reset is applied)...Retains the state immediately before the STP or WIT instruction was executed. ? RW V3 00 0 V1 V2 V3 V4 (Reserved area) V4 Memory allocation control register UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Oscillation circuit control register 1 RW ? 0 00 0 RW ? 00 0 000 0 WO WO WO RW RO 1 00 0 RW RO RW RO 00 0 0 0 1 0 0 RO 0 0 0 00 0 ? RW ? ? 0 00 0 0 00 0 ? 0 13.1 Hardware reset Fig. 13.1.6 State of SFR area and internal RAM area immediately after reset (4) |
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