7733 datasheet(575/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21-27

Appendix 3. Control registers

sPulse period/Pulse width measurement mode

b0 b7

(b15)

(b8)

Timer B0 register (addresses 5116, 5016)

Timer B1 register (addresses 5316, 5216)

Timer B2 register (addresses 5516, 5416)

Functions

Bit

At reset

15 to 0 The result of the pulse period or pulse width

measurement is read out.

Un-

defined

0 0: Pulse period m easurem ent

Interval betw een falling edges of the

m easurem ent pulse)

0 1: Pulse period m easurem ent

Interval betw een risi ng edges of the

m easur

ement pulse)

1 0: Pulse width m easurem ent

Interval from a falling edge to a risi ng edge,

and from a risi ng edge to a falling edge of

the measurement pulse)

1 1: Do not sel ect .

Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16)

Bit

Count source selection bits

Timer Bi overflow flag (Note)

•Timer B0 mode register

Must be fixed to “0.”

Measurement mode selection

bits

Operating mode selection bits

Bit name

Functions

1 0: Pulse period/pulse width m easurem ent

m ode

b1 b0

0: No overflow

1: Overflow

b3 b2

0 0: Clock f2

0 1: Clock f16

1 0: Clock f64

1 1: Clock f512

b7 b6

At reset

Un-

defined

•Timer B1 and B2 mode registers

Not implemented.

Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

Note: Timer Bi overflow flag is cleared to “0” when writing to the timer Bi mode register is performed with the

count start flag = “1.” This flag cannot be set to “1” by software.

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