7733 datasheet(577/940 Pages) RENESAS

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APPENDIX

7733 Group User’s Manual

21-29

Appendix 3. Control registers

Processor mode register 0

Bit

Bit name

Functions

At reset

Processor mode bits

Wait bit

Software reset bit

Must be fixed to “0.”

Clock

f 1 output selection bit

(Note 2)

0 0: Single-chip mode

0 1: Memory expansion mode

1 0: Microprocessor mode

1 1: Do not select.

0: Software wait is inserted when

accessing external area.

1: No software wait is inserted

when accessing external area.

Microcomputer is reset by

setting this bit to “1.”

This bit is “0” at reading.

0 0: 7 cycles of

0 1: 4 cycles of

1 0: 2 cycles of

1 1: Do not select.

0: Clock

f 1 output is disabled.

(P42

functions as a

programmable I/O port.)

1: Clock

f 1 output is enabled.

functions as a clock

f 1 output pin.)

b1 b0

b5 b4

Processor mode register 0 (address 5E16)

(Note 1)

Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset.

(At reading, this bit is always “1.”)

2: This bit is ignored in the microprocessor mode. (It may be “0” or “1.”)

Interrupt priority detection

time selection bits

Processor mode register 1

Processor mode register 1 (address 5F16)

Bit

Bit name

Function

At reset

7 to1

Wait selection bit

0 : Wait 0

1 : Wait 1

Not implemented.

Un-

defined

(Port P4

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