7733 datasheet(670/940 Pages) RENESAS

670 / 940 page

STOP AND WAIT MODES

7735 Group User’s Manual

11–2

11.2 Clock generating circuit

Concerning chapter “11. STOP AND WAIT MODES,” the 7735 Group differs from the 7733 Group in the

following sections. Therefore, only the differences are described in this chapter:

• “11.2 Clock generating circuit”

• “11.3 Stop mode”

• “11.4 Wait mode”

The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section,

refer to part 1:

• “11.1 Overview” (page 11-2 in part 1)

11.2 Clock generating circuit

Concerning section “11.2 Clock generating circuit,” the 7735 Group differs from the 7733 Group in the

following:

• Figures 11.2.3 and 11.2.4

The other description is the same as that of the 7733 Group. Therefore, refer to part 1:

• “11.2 Clock generating circuit” (page 11-3 in part 1)

In the M37735MHBXXXFP, be sure to set bit 3 of the oscillation circuit control register 1 to “0.”

Fig. 11.2.3 Structure of oscillation circuit control register 1

2: Because this bit is “1” at reset, clear this bit to “0” with the initial setting program after

reset.

3: The case where data “01010101 2” is written with the procedure shown in Figure 11.2.4.

is not included.

4: For the 7733 Group, refer to Figure 11.2.3 in part 1.

represents that bits 3 to 7 are not used for the stop and wait modes.

Bit

Bit name

Functions

At reset

Main clock division selection bit

Sub clock external input selection bit

Must be fixed to “0” in the one time PROM and EPROM versions (Notes 1 and 2).

Must be fixed to “0” (Note 3).

Clock prescaler reset bit

Undefined

Oscillation circuit control register 1 (address 6F 16)

0: Sub-clock oscillation circuit is operating

by itself. Pin P76 functions as pin XCOUT.

Watchdog timer is used when

terminating stop mode.

1: Sub clock is input from the external.

Pin P76 functions as a programmable

I/O port. Watchdog timer is not used when

terminating stop mode.

—

Not implemented.

Notes 1: When writing to this register, follow the procedure shown in Figure 11.2.4.

By writing “1” to this bit, clock prescaler is

initialized.

(Note 4)

Undefined

Main clock external input selection bit

0: Main clock is divided by 2.

1: Main clock is not divided by 2.

0: Main-clock oscillation circuit is operating by

itself. Watchdog timer is used when

terminating stop mode.

1: Main clock is input from the external.

Watchdog timer is not used when

terminating stop mode.

Must be fixed to “0” in the mask ROM and external ROM versions (Note 1).

(Note 1)

7733 Datasheet(PDF) 670 Page - Renesas Technology Corp

7733 Datasheet(HTML) 670 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL