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7733 Datasheet(PDF) 672 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 672 Page - Renesas Technology Corp |
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672 / 940 page ![]() STOP AND WAIT MODES 7735 Group User’s Manual 11–4 Table 11.3.2 Pin state in stop mode State Single-chip mode Memory expansion Microprocessor mode mode Pins When the standby state selection bit∗1 = “0” When the standby state selection bit∗1 = “1” s When the signal output disable selection bit = “0,” “H” level is output s When the signal output disable selection bit = “1,” “L” level is output. s When the signal output disable selection bit = “0,” “H” level is output. s When the signal output disable selection bit = “1,” “L” level is output. Same as in the micro- processor mode “H” level is output. __ E ____ RDE, ____ WEL, ____ WEH, ____ ____ CS0 –CS4, _____ RSMP, _____ HLDA ALE A0/D0–A15/D15, A16, A17 Output levels can be set. (Refer to section “11.3.1 Output levels of external bus and bus control signals in stop mode.”) 11.3 Stop mode “L” level is output. s When the clock φ1 output selection bit*2 = “1” φ1: “L” level is output. s When the clock φ1 output selection bit = “0” P42: Retains the same state in which the STP instruction is executed. Retains the same state in which the STP instruction is executed. s When the signal output disable selection bit*3 = “0” φ1: “L” level is output. s When the signal output disable selection bit = “1” P42: Bit 2’s value of the port P4 register is output (Note). P0 to P8 (not including P42) : Retains the same state in which the STP instruction is executed. P43 to P47, P5 to P8 :Retains the same state in which the STP instruction is executed. Ports P42/ φ1 Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.3.1.) Clock φ1 output selection bit*2: Bit 7 at address 5E16 (Refer to section “12.1 Signals required for accessing external devices.”) Signal output disable selection bit*3: Bit 6 at address 6C16 (Refer to section “12.1 Signals required for accessing external devices.”) Note: Make sure to set bit 2 of the port P4 direction register to “1.” |
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