7733 datasheet(693/940 Pages) RENESAS

693 / 940 page

of the external area.

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual

12–17

Fig. 12.2.1 Structures of processor mode register 0 and processor mode register 1

Processor mode register 1 (address 5F 16)

Bit

Bit name

Function

At reset

7 to1

Wait selection bit

0 : Wait 0

1 : Wait 1

Not implemented.

Un-

defined

Bit

Bit name

Functions

At reset

Processor mode bits

Wait bit

Software reset bit

Interrupt priority detection

time selection bits

Must be fixed to “0.”

Clock f1 output selection bit

(Note 2)

00: Single-chip mode

01: Memory expansion mode

10: Microprocessor mode

11: Do not select.

0: Software wait is inserted when

accessing external area.

1: No software wait is inserted

when accessing external area.

Microcomputer is reset by

setting this bit to “1.”

This bit is “0” at reading.

00: 7 cycles of

01: 4 cycles of

10: 2 cycles of

11: Do not select.

0: Clock

f1 output is disabled.

(P4 2 functions as a

programmable /O port.)

1: Clock

f1 output is enabled.

(Port P4 2 functions as a clock

output pin.)

b1 b0

b5 b4

Processor mode register 0 (address 5E 16)

(Note 1)

Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset.

(At reading, this bit is always “1.”)

2: This bit is ignored in the microprocessor mode. (It may be “0” or “1.”)

represents that bits 3 to 6 are not used for access control

(Functions of these bits are valid.)

12.2 Software wait

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