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7733 Datasheet(PDF) 695 Page - Renesas Technology Corp

Part # 7733
Description  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7733 Datasheet(HTML) 695 Page - Renesas Technology Corp

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CONNECTING EXTERNAL DEVICES
7735 Group User’s Manual
12–19
P42/
φ1
Timers A and B, Serial I/O,
A-D converter,
Watchdog timer
Item
State
12.3 Ready function
The ready function facilitates access to external devices which require a long access time.
____
By applying “L” level to pin RDY in the memory expansion or microprocessor mode, the microcomputer
____
enters the ready state. While pin RDY’s level is “L,” this state is retained. Table 12.3.1 lists the microcomputer’s
state in the ready state.
In the ready state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can
operate even in the ready state. The ready function is valid for the internal and external areas.
Table 12.3.1 Microcomputer’s state in ready state
Clock
φ1 output selection bit*1: Bit 7 at address 5E16
Signal output disable selection bit*2: Bit 6 at address 6C16
____
Notes 1: When “L” level which was input to pin RDY is sampled at one of the following timings, this signal
is not accepted. (Note that
φCPU is stopped at “L” level.)
____
____
____
q When the levels of signals RDE, WEL, and WEH are “H” while the bus is in use (Refer to  in
Figure 12.3.2.)
q Immediately before a wait generated by the software wait (Refer to  in Figure 12.3.2.)
2: This is applied when these pins function as programmable I/O ports.
Oscillation
φCPU
Operating
Stopped at “L” level
____
Retains the same state in which RDY was accepted.
In the memory expansion mode
s When the clock
φ1 output selection bit*1 = “1”
Outputs clock
φ1.
s When the clock
φ1 output selection bit = “0”
____
Retains the same state in which RDY was accepted.
In the microprocessor mode
s When the signal output disable selection bit*2 = “1”
____
Retains the same state in which RDY was accepted.
s When the signal output disable selection bit = “0”
Outputs clock
φ1.
Operating
____
____
____
RDE
, WEL, WEH, CS0
to CS4,
_____
HLDA
, ALE, A 0/D0 to A 15/D15,
A16, A17
P43 to P47, P5 to P8 (Note 2)
12.3 Ready function



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