7733 datasheet(700/940 Pages) RENESAS

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CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual

12–24

Clock

ALE

At reading

At writing

RDE

q Determination timing of pin HOLD’s input level

Not

determined

Determined

Word data is accessed by the two bus cycles.

(in this case, no wait)

12.4.1 Operation in hold state

_____

When “L” level is input to pin HOLD while the bus is not in use, this signal is accepted at the falling edge

_____

of clock

φ1. When “L” level is input to pin HOLD while the bus is in use, this signal is accepted at the clock

____

φ1’s falling edge which precedes the rising edge of signal RDE, WEL, or WEH by the clock φ1’s cycle divided

by 2. (Refer to Figures 12.4.2 to 12.4.6.) Note that when word data which starts from an odd address is

accessed by the two bus cycles, determination is performed only in the second bus cycle. (Refer to Figure

12.4.1.)

_____

When “L” level which was input to pin HOLD is accepted,

φCPU is stopped at the next rising edge of clock

_____

φ1. At this time, pin HLDA outputs “L” level, and so the external is informed that the microcomputer is in

_____

____

the hold state. After one cycle of clock

φ1 has passed since pin HLDA’s level becomes “L,” pins RDE, WEL,

____

_____

WEH

, CS0 to CS4, RSMP and the external bus enter the floating state.

_____

The hold state can be terminated by setting pin HOLD’s level to “H” again. When “H” level is input to pin

_____

HOLD

, this signal is accepted at the falling edge of clock

φ1. When “H” level which was input to pin HOLD

_____

is accepted, pin HLDA’s level goes from “L” to “H.” And then, the hold state is terminated after one cycle

of clock

φ1 has passed.

Figures 12.4.2 to 12.4.6 show the timing when the hold state is accepted and terminated.

_____

g In the ready state, determination of pin HOLD’s input level is not performed.

Fig.12.4.1 Determination when word data which starts from odd address is accessed by the two bus cycles

12.4 Hold function

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