7733 datasheet(166/940 Pages) RENESAS

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TIMER B

7733 Group User’s Manual

7–3

7.2 Block description

Figure 7.2.1 shows the timer B block diagram. Registers related to timer B are described below.

Fig. 7.2.1 Timer B block diagram

f16

f64

f512

Clock source selection

•Timer mode

•Pulse period/Pulse width measurement mode

Polarity switching

and Edge pulse

generating circuit

Event counter mode

Count start flag

Counter reset circuit

Data bus (Odd)

Data bus (Even)

(Low-order 8 bits)

(High-order 8 bits)

Timer Bi reload register (16)

Timer Bi counter (16)

Timer Bi

interrupt request bit

TBiIN

(i = 0 to 2)

Timer Bi overflow

flag

fc32 (Note 1)

TB2 overflow

signal (Note 2)

(address 4016)

addresses

Timer B0 5116 5016

Timer B1 5316 5216

Timer B2 5516 5416

Notes 1: Clock source for clock timer

Can be selected only for TB2 (Refer to Figure 14.3.1.)

2: Can be selected only for TB1 (Internal connect mode)

Clocks f2, f16, f64, and f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

7.2 Block description

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