7733 datasheet(170/940 Pages) RENESAS

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TIMER B

7733 Group User’s Manual

7–7

7.2.4 Timer Bi interrupt control register

Figure 7.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer

to chapter “4. INTERRUPTS”

Fig. 7.2.4 Structure of timer Bi interrupt control register

(1) Interrupt priority level selection bits (bits 2 to 0)

These bits select a timer Bi interrupt’s priority level. When using timer Bi interrupts, select one priority

level from levels 1 to 7. If a timer Bi interrupt request is generated, its priority level is compared with

the processor interrupt priority level (IPL), and then the requested interrupt is enabled only when its

priority level is higher than the IPL. (However, this is applied when the interrupt disable flag (I) = “0.”)

When disabling timer Bi interrupts, set these bits to “0002” (Level 0).

(2) Interrupt request bit (bit 3)

This bit is set to “1” when a timer Bi interrupt request is generated. This bit is automatically cleared

to “0” when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by

software.

At reset

Bit

7 to 4

Not implemented.

Interrupt priority level selection

bits

Bit name

Un-

defined

—

Functions

0 0 0: Level 0 (Interrupt is disabled.)

0 0 1: Level 1

Priority is low.

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

Priority is high.

b2 b1 b0

0: No interrupt request has occurred.

1: Interrupt request has occurred.

Timer Bi interrupt control register (i = 0 to 2)

(addresses 7A16 to 7C16)

Interrupt request bit

7.2 Block description

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