7733 datasheet(221/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–18

At reset

Bit

7 to 4

Not implemented.

Interrupt request bit

Interrupt priority level selection

bits

Bit name

Un-

defined

(Note)

—

Functions

0 0 0: Level 0 (Interrupt is disabled.)

0 0 1: Level 1

Priority is low.

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

Priority is high.

b2 b1 b0

0: No interrupt has occurred.

1: Interrupt has occurred.

A-D/UART2 trans./rece. interrupt control register (address 70 16)

UART0 transmission interrupt control register (address 71 16)

UART0 receive interrupt control register (address 72 16)

UART1 transmission interrupt control register (address 73 16)

UART1 receive interrupt control register (addresses 74 16)

Note: When the UART2 function is selected, bit 3 of the A-D conversion/UART2 trans./rece. interrupt

control register is set to “1.”

Accordingly, before enabling interrupts, write value “0” to this bit.

8.2.8 Interrupt control register related to UARTi

When UARTi is used, the following interrupts can be used: UARTi transmission interrupt and UARTi

reception interrupt. Each interrupt has its corresponding interrupt control register. However, in UART2, an

interrupt for transmission and an interrupt for reception are controlled with the same register. Figure 8.2.15

shows the structure of interrupt control registers related to UARTi.

For details about interrupts, refer to chapter “4 Interrupts.”

The UART2 transmission/reception interrupt and the A-D conversion interrupt share the same interrupt

vector addresses and interrupt control register.

Switching between the A-D conversion interrupt and the UART2 transmission/reception interrupt is performed

with bits 2 to 0 of the UART2 transmission/reception mode register. (Refer to Figure 8.2.3.)

8.2 Block description

Fig. 8.2.15 Structure of interrupt control registers related to UARTi

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