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7733 Datasheet(PDF) 223 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 223 Page - Renesas Technology Corp |
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223 / 940 page ![]() SERIAL I/O 7733 Group User’s Manual 8–20 8.2.9 Ports P7 and P8 direction registers I/O pins of UARTi are multiplexed with ports P7 and P8. When using the P74, P82 and P86 pins as serial data input pins (RxDi), set the corresponding bits of the ports P7 and P8 direction registers to “0” to set _____ these ports for the input mode. When using the P72 pin as the CTS2 input pin, set bit 2 of the port P7 direction register to “0” to set this port for the input mode. When using the P73, P75, P80, P81, P83–P85, _________ _________ and P87 pins as UARTi’s I/O pins (CTSi/RTSi, CLKi, TxDi), these pins are forcibly set as the UARTi’s I/O pins, regardless of the ports P7 and P8 direction register’s contents. Also, as for CLKS0 and CLKS1, refer to section “8.3.1 (4) Number of transfer clock output pins (UART0).” Figure 8.2.16 shows the relationship between the ports P7, P8 direction registers and UARTi’s I/O pins. Note that the functions of the UARTi’s I/O pins can be switched by software. For details, refer to the description of each operating mode. 8.2 Block description Bit Corresponding pin name Functions 0 1 2 3 4 5 6 7 Pin P74/AN4/RxD2 Pin P76/AN6/XCOUT 0: Input mode 1: Output mode When using pin P72 as the CTS2 input pin and using pin P74 as serial data’s input pin (RxD2), set the corresponding bit to “0.” Pin P75/AN5/ADTRG/TxD2 Port P7 direction register (address 1116) b1 b0 b2 b3 b4 b5 b6 b7 Pin P70/AN0 Pin P72/AN2/CTS2 Pin P73/AN3/CLK2 Pin P71/AN1 Pin P77/AN7/XCIN At reset RW 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 Pin P80/CTS0/RTS0/CLKS1 Pin P82/RxD0/CLKS0 Pin P83/TxD0 Pin P84/CTS1/RTS1 Pin P86/RxD1 Pin P85/CLK1 Port P8 direction register (address 1416) b1 b0 b2 b3 b4 b5 b6 b7 Pin P81/CLK0 Pin P87/TxD1 RW 0 0 0 0 0 0 0 0 Not used for serial I/O Corresponding pin name Functions Bit At reset 0: Input mode 1: Output mode When using pins P82 and P86 as serial data’s input pins (RxD0, RxD1), set the corresponding bits to “0.” RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Note: For pins CLKS0 and CLKS1, refer to section “8.3.1 (4) Number of transfer clock output pins (UART0).” Fig. 8.2.16 Relationship between ports P7, P8 direction register and UARTi’s I/O pins : |
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