7733 datasheet(226/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–23

TXDi

RXDi

CLKi

TXDi

RXDi

CLKi

When CLK polarity selection bit = “1.”

g The transmit data is output to the TxDi pin at the rising edge of the transfer clock; the receive data is input from the RxDi

pin at the falling edge of the transfer clock.

When not transferring, the CLKi pin’s level is “L.”

When CLK polarity selection bit = “0.”

g The transmit data is output to the TxDi pin at the falling edge of the transfer clock; the receive data is input from the RxDi

pin at the rising edge of the transfer clock.

When not transferring, the CLKi pin’s level is “H.”

(3) How to select polarity of transfer clock

The polarity of a clock which is output from the CLKi pin can be selected with the CLK polarity

selection bit (UART0, UART1) as shown in Figure 8.3.1. The CLK polarity select bit is not implemented

for UART2. The CLK2 pin outputs the transmit data at the fall of the transfer clock; this pin inputs the

receive data at the rise of the transfer clock.

[Setting for related registers]

q The CLK polarity is selected (bit 6 at addresses 3416, 3C16).

Fig. 8.3.1 Polarity of transfer clock

8.3 Clock synchronous serial I/O mode

7733 Datasheet(PDF) 226 Page - Renesas Technology Corp