7733 datasheet(228/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–25

[Switching of transfer clock output pin]

When the transfer clock output pin is switched while transmission is enabled, follow the procedure described

below. Transmission starts when step is executed:

Check whether the previous transfer is completed or not. (Refer to Figure 8.3.6.)

If the previous transfer has been completed, change the contents of the transmit clock output pin

selection bit.

Set the transmit data.

For usage examples, refer to section “17.2.2 Examples of transmission for several peripheral ICs

(Clock synchronous serial I/O mode).”

Table 8.3.4 Number of channels for serial I/O transmission/reception for the case where multiple

transfer clock output pins are used

____

CTS0

/RTS0/CLKS1 (P80)

CLK0 (P81)

RxD0/CLKS0 (P82)

TxD0 (P83)

•Number of channels for

serial I/O transmission/

reception

•Status of transmit clock

output pin selection bits

(b5, b4)

Setting example

Outputs transfer clock.

Receives data.

Transmits data.

1 channel for transmission

CLKS1

TxD0

1 channel for

transmission/reception

CLK0

RxD0

TxD0

Programmable I/O port

Outputs transfer clock.

Transmits data.

2 channels for transmission

CLK0

TxD0

CLKS0

TxD0

Outputs transfer clock.

Transmits data.

3 channels for transmission

CLKS1

TxD0

CLK0

TxD0

CLKS0

TxD0

(1, 1)

(0, 1)

(1, 0)

(0, 1)

(1, 0)

(1, 1)

(0, 1)

Note: Set bit 2 at address 1416 (port P8 direction register) to “0.”

8.3 Clock synchronous serial I/O mode

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