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7733 Datasheet(PDF) 270 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 270 Page - Renesas Technology Corp |
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270 / 940 page ![]() A-D CONVERTER 7733 Group User’s Manual 9–5 0 f2 divided by 4 15.68 18.88 A-D conversion frequency ( φAD) selection flag φAD Conversion time Resolution : 8 bits •System clock = 25 MHz (Note) Resolution : 10 bits 1 f2 divided by 2 7.84 9.44 (2) Trigger selection bit (bit 5) This bit selects a trigger occurrence source. (Refer to “(3) A-D conversion start flag.”) (3) A-D conversion start flag (bit 6) When internal trigger is selected When this bit is set to “1,” a trigger occurs, and then the A-D converter starts operating. When this bit is cleared to “0,” the A-D converter stops operating. In the one-shot or single sweep mode, this bit is cleared to “0” after A-D conversion is completed. In the repeat or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. When external trigger is selected ______ If the ADTRG pin level goes from “H” to “L” when this bit = “1,” a trigger occurs, and then the A-D converter starts operating. The A-D converter stops operating when this bit is cleared to “0.” In the one-shot or single sweep mode, this bit remains set to “1” even after A-D conversion is completed. In the repeat or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. (4) A-D conversion frequency ( φAD) selection flag (bit 7) Conversion time varies according to the A-D converter’s operating clock ( φAD) selected by this bit as listed in Table 9.2.1. Since the A-D converter’s comparator consists of capacity coupling amplifiers, keep that φAD ≥ 250 kHz during A-D conversion. Note: This is applied when the following conditions are satisfied; •f(XIN) = 25 MHz •The main clock is selected as the system clock. •Main clock divided by 2 is available. Table 9.2.1 Conversion time per one analog input pin (Unit: µs) 9.2 Block description |
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