7733 datasheet(273/940 Pages) RENESAS

273 / 940 page

A-D CONVERTER

7733 Group User’s Manual

9–8

Bit

7 to 4

Not implemented.

Interrupt request bit (Note)

Interrupt priority level selection

bits

Bit name

At reset

Undefined

Functions

0 0 0: Level 0 (Interrupt is disabled.)

0 0 1: Level 1

Priority is low.

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

Priority is high.

b2 b1 b0

0: No interrupt request has occurred.

1: Interrupt request has occurred.

A-D/UART2 trans./rece. interrupt control register (address 70 16)

Note: When UART2 is selected, in other words, when a serial I/O mode is selected by specifying

the serial I/O mode selection bits (bits 0 to 2 at address 64 16), this bit is set to “1.”

9.2.4 A-D/UART2 trans./rece. interrupt control register

Figure. 9.2.5 shows the structure of the A-D/UART2 trans./rece. control register.

The A-D conversion interrupt and UART2 transmission/reception interrupt share the same interrupt control

When UART2 is selected, the A-D/UART2 trans./rece. interrupt control register functions as an register

which control the UART2 transmission/reception interrupt. At this time, the A-D conversion interrupt cannot

be used.

For details on interrupts, refer to chapter “4. INTERRUPTS.” For details on UART2, refer to chapter “8.

SERIAL I/O.”

The case where this register is used as the A-D conversion interrupt control register is described below.

Fig. 9.2.5 Structure of A-D/UART2 trans./rece. interrupt control register

9.2 Block description

–

7733 Datasheet(PDF) 273 Page - Renesas Technology Corp