7733 datasheet(305/940 Pages) RENESAS

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WATCHDOG TIMER

7733 Group User’s Manual

10-8

10.2 Operation description

10.2.4 Operation in hold state

The watchdog timer stops operating in the hold state. (Refer to section “12.4 Hold function.”) When the

hold state is terminated, the watchdog timer restarts counting from the same state as that before the

watchdog timer stops.

Fig. 10.2.1 Structure of oscillation circuit control register 0

Bit

Bit name

Functions

At reset

XCOUT drivability selection bit

Main clock stop bit

System clock selection bit

Port-Xc selection bit

Not implemented.

Un-

defined

0: Drivability “LOW”

1: Drivability “HIGH”

When the port-Xc selection bit = “0,”

0: Main clock

1: Main clock divided by 8

When the port-Xc selection bit = “1,”

0: Main clock

1: Sub clock

Un-

defined

Oscillation circuit control register 0 (address 6C16)

Notes

0: Main clock oscillation or external clock

input is available.

1: Main clock oscillation or external clock

input is stopped.

Not implemented.

(Note 1)

0: Operate as I/O ports (P77, P76).

1: Operate as pins XCIN and XCOUT.

(Notes 2

and 3)

(Note 2)

System clock stop bit at wait state

0: Output is enabled.

1: Output is disabled.

(Refer to Tables

12.1.2 and 12.1.5)

0: Operates in the wait mode.

1: Stopped in the wait mode.

Signal output disable selection bit

(Note 1)

1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc

selection bit = “1.”

2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.”

If the above settings are performed simultaneously, in other words, performed by

executing only one instruction, only bit 3 is set to “1.”

3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.”

represents that bits 0 to 2 and bit 7 are not used for the watchdog timer.

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