7733 datasheet(306/940 Pages) RENESAS

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WATCHDOG TIMER

7733 Group User’s Manual

10-9

Fig. 10.2.2 Structure of oscillation circuit control register 1

Fig. 10.2.3 Procedure for writing data to oscillation circuit control register 1

10.2 Operation description

Bit

Bit name

Functions

At reset

Main clock division selection bit

Sub clock external input selection bit

Must be fixed to “1” in the one time PROM and EPROM versions (Notes 1 and 2).

Must be fixed to “0” (Note 2).

Clock prescaler reset bit

Undefined

Oscillation circuit control register 1 (address 6F16)

0: Sub-clock oscillation circuit is operating by

itself. Pin P76 functions as pin XCOUT.

Watchdog timer is used when terminating

stop mode.

1: Sub clock is input from the external.

Pin P76 functions as a programmable

I/O port. Watchdog timer is not used when

terminating stop mode.

—

Not implemented.

Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3.

By writing “1” to this bit, clock prescaler is

initialized.

(Note 3)

Undefined

Main clock external input selection bit

0: Main clock is divided by 2.

1: Main clock is not divided by 2.

0: Main-clock oscillation circuit is operating by

itself. Watchdog timer is used when terminating

stop mode.

1: Main clock is input from the external.

Watchdog timer is not used when

terminating stop mode.

Ignored in the mask ROM and external ROM versions.

2: The case where data “010101012” is written with the procedure shown in Figure 10.2.3

is not included.

3: In the 7735 Group, fix this bit to “0.”

represents that bits 3 to 7 are not used for the watchdog timer.

(Note 1)

Write data “010101012.” (LDM instruction)

• When writing to bits 0 to 3

Write data “00001XXX2.” (LDM instruction)

Next instruction

(b3 in Figure 10.2.2)

(b2 to b0 in Figure 10.2.2)

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