7733 datasheet(331/940 Pages) RENESAS

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CONNECTING EXTERNAL DEVICES

7733 Group User’s Manual

12–6

12.1.2 External data bus width selection signal (Pin BYTE’s level)

This signal is used to select the external data bus width from 8 bits and 16 bits. When this signal level

is “L,” the external data bus is 16 bits wide; when this signal level is “H,” the external data bus is 8 bits

wide. (Refer to Table 12.1.1.) This signal level must be fixed to either “H” or “L.”

This signal is valid only for the external areas. (When the internal area is accessed, the data bus is always

16 bits wide.)

12.1.3 Enable signal (E)

When data is read or written, this signal level is “L.” This signal is affected by the signal output disable

selection bit (bit 6 at address 6C16). (Refer to Table 12.1.2.)

Table 12.1.2 E state

When the external area is accessed

When the internal area is accessed

When the standby state selection bit

= “1” in the stop or wait mode

When the standby state selection bit

= “0” in the stop or wait mode

When not in the stop or wait mode

When in the stop or wait mode

Signal output disable selection bit

Memory expansion or

Microprocessor mode

Single-chip mode

Processor

mode

Conditions

Table 12.1.3 Data bus state

R/W

Data bus state

Not used

Read

Write

For the stop and wait modes and the standby state selection bit, refer to chapter “11. STOP AND WAIT

MODES.”

: Not affected by the signal output disable selection bit.

12.1.4 Read/Write signal (R/W)

This signal indicates data bus state. When data is written, this signal level is “L.” Table 12.1.3 lists the data

bus state indicated by signals E and R/W.

Operating

Stopped at “H” level

Stopped at “H” level Stopped at “L” level

Stopped at “H” level

Operating

Stopped at “L” level

Stopped at “H” level Stopped at “L” level

12.1 Signals required for accessing external devices

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