7733 datasheet(332/940 Pages) RENESAS

332 / 940 page

CONNECTING EXTERNAL DEVICES

7733 Group User’s Manual

12–7

____

12.1.5 Byte high enable signal (BHE)

This signal indicates access to an odd address. This signal level is “L” when accessing only an odd

address or when simultaneously accessing both an odd address and an even address.

This signal is used when connecting memory or I/O of which data bus is 8 bits wide with the 16-bit external

data bus used. Table 12.1.4 lists the relationship between signal A0 of the external address bus, signal

____

BHE

, and access address.

____

Table 12.1.4 Relationship between signals A0, BHE and access address

____

BHE

Access address

Odd address

(1-byte access)

Even and Odd addresses

(Simultaneous 2-byte access)

Even address

(1-byte access)

12.1.6 Address latch enable signal (ALE)

This signal is used to latch an address from a multiplexed signal. This multiplexed signal consists of the

address and data and is input or output to or from pins A8/D8 to A15/D15, A16/D0 to A23/D7. When this signal

level is “H,” take the address into a latch and output it simultaneously. When this signal level is “L,” retain

the latched address.

____

12.1.7 Signal related to ready function (RDY)

This signal is required to use the ready function. (Refer to section “12.3 Ready function.”)

_____

12.1.8 Signals related to hold function (HOLD, HLDA)

These signals are required to use the hold function. (Refer to section “12.4 Hold function.”)

12.1.9 Clock

φ1

This signal has the same period as internal clock

φ.

Whether to output or stop clock

φ1 can be selected by software. However, the method of this selection

depends on the processor mode. Table 12.1.5 lists the method to select whether to output or stop clock

φ1. Figure 12.1.3 shows the clock φ1 output start timing.

Table 12.1.5 Method to select whether to output or stop clock

φ1

Clock

φ1 output

Clock

φ1 stopped

Remark

Processor mode

Single-chip or Memory expansion mode

Microprocessor mode

Clear the signal output disable

selection bit*2 to “0.”

Set the signal output disable

selection bit to “1.” (Note)

Clock

φ1 is output after reset.

The clock

φ1 output selection bit is

ignored.

Set the clock

φ1 output selection bit*1 to

“1.”

Clear the clock

φ1 output selection bit to

“0.” (Pin P42 functions as a programmable

I/O port.)

Clock

φ1 is stopped after reset.

The signal output disable selection bit is

ignored.

Clock

φ1 output selection bit*1: Bit 7 at address 5E16

Signal output disable selection bit*2: Bit 6 at address 6C16 (Refer to Table 12.1.2.)

Note: In this case, make sure that bit 2 at address C16 (Port P4 direction register) is set to “1.”

When bit 2 at address A16 (Port P4 register) = “0,” “L” level is output: when this bit = “1,” “H” level

is output.

12.1 Signals required for accessing external devices

7733 Datasheet(PDF) 332 Page - Renesas Technology Corp

7733 Datasheet(HTML) 332 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL