7905 datasheet(68/565 Pages) RENESAS

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CLOCK GENERATING CIRCUIT

7905 Group User’s Manual Rev.1.0

4-7

–

4.2 Clocks

(3) System clock select bit (bit 5)

This bit selects a clock source of fsys. When this bit = “0,” fXIN is selected as fsys; and when this bit =

“1,” fPLL as the one. (See Table 4.2.1.)

Clearing the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also,

while the PLL circuit operation enable bit = “0,” nothing can be written to the system clock select bit.

(Fixed to be “0.”)

In order to set the system clock select bit to “1” after reset, it is necessary to wait 2 ms after the

stabilization of f(XIN).

To rewrite the PLL multiplication ratio select bits (bits 2 and 3), clear the system clock select bit to

“0” simultaneously. Then, set this bit to “1” 2 ms after the rewriting of the PLL multiplication ratio select

bits. (See Figure 4.2.3.)

System clock select bit

(bit 5)

PLL multiplication ratio select bits

(bits 3, 2) (Note 1)

fsys

–

01 (double)

10 (triple)

11 (quadruple)

f(XIN)

f(XIN) ✕ 2

f(XIN) ✕ 3

f(XIN) ✕ 4

PLL circuit operation

enable bit (bit 1)

Clock source Frequency (Note 2)

fXIN

fPLL

fsys/2

fsys/4

fsys/32

fsys/128

fsys/1024

fsys/8192

Do not select.

Internal peripheral

device’s operation clock

Peripheral device’s clock select bits 1, 0

f16

f64

f512

f4096

fsys

fsys/2

fsys/16

fsys/64

fsys/512

fsys/4096

fsys

fsys/8

fsys/32

fsys/256

fsys/2048

(Note)

Table 4.2.1 fsys selection

Notes 1: The PLL multiplication ratio select bits must be set so that fsys is in the range from 10 MHz to 20 MHz. After

reset, these bits are allowed to be changed only once.

2: Be sure that fsys does not exceed 20 MHz.

Table 4.2.2 Internal peripheral device’s operation clock frequency

(4) Peripheral device’s clock select bits 1, 0 (bits 7, 6)

These bits select the internal peripheral device’s operation clock frequency listed in Table 4.2.2.

Note: To set the peripheral device’s clock select bits 1, 0 to “012,” be sure that a frequency of fsys must be 10 MHz or less.

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