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7905 Group User’s Manual Rev.1.0

2.1 Central processing unit (CPU)

CENTRAL PROCESSING UNIT (CPU)

2-9

(6)

Bit 5: Data length flag (m)

This flag determines whether to use data as a 16-bit unit or as an 8-bit unit. Each data is treated

as a 16-bit unit when this flag is “0,” and as an 8-bit unit when it is “1” (Note).

Be sure to use the SEM or SEP instruction to set this flag to “1,” and be sure to use the CLM or

CLP instruction to clear it to “0.”

This flag is cleared to “0” at reset.

Note: When transferring data between registers which are different in bit length, this data is transferred

with the length of the transfer destination register, except for the case where the TXA, TYA,

TXB, TYB, and TXS instructions used. Refer to “7900 series software manual” for detail.

(7)

Bit 6: Overflow flag (V)

This flag is used when addition or subtraction is performed with a word regarded as signed binary.

The overflow flag is set to “1” when the result of addition or subtraction exceeds the range between

–2147483648 and +2147483647 (when 32-bit length operation), the range between –32768 and

+32767 (when 16-bit length operation), or the range between –128 and +127 (when 8-bit length

operation).

The overflow flag is also set to “1” when the operation result of the DIV or DIVS instruction exceeds

the length of the register which will store that result. This flag is invalid in the decimal mode. Be sure

to use the SEP instruction to set this flag to “1,” and be sure to use the CLV or CLP instruction to

clear it to “0.”

The contents of this flag is undefined at reset.

(8)

Bit 7: Negative flag (N)

This flag is set to “1” when the result of arithmetic operation or data transfer is negative. (The most

significant bit of the result is “1.”) It is cleared to “0” in all other cases. This flag is invalid in the

decimal mode. Be sure to use the SEP instruction to set this flag to “1,” and be sure to use the CLP

instruction to clear it to “0.”

The contents of this flag is undefined at reset.

(9)

Bits 10 to 8: Processor interrupt priority level (IPL)

These 3 bits can determine the processor interrupt priority level to one of levels 0 through 7. When

the interrupt priority level of a requested interrupt, which has been set in the corresponding interrupt

control register, is higher than IPL, that interrupt becomes enabled. When an interrupt request is

accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the

accepted interrupt request.

There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the

new IPL into the stack area and updating PS with the PUL or PLP instruction.

The contents of IPL is cleared to “0002” at reset.

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