7905 datasheet(83/565 Pages) RENESAS

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7905 Group User’s Manual Rev.1.0

INTERRUPTS

6-2

When an interrupt request is accepted, the following

registers’ contents just before acceptance of an

interrupt request are automatically pushed onto the

stack area in ascending sequence from ➀ to ➂.

For other registers of which contents are necessary,

be sure to push and pop them by software.

➀ Program bank register (PG)

➁ Program counter (PCL, PCH)

➂ Processor status register (PSL, PSH)

Figure 6.1.2 shows the state of the stack area just

before entering an interrupt routine.

Execute the RTI instruction at the end of this interrupt

routine in order to return to the routine that the

microcomputer was executing just before the interrupt

request was accepted. By executing the RTI instruction,

the register contents pushed onto the stack area are

pulled in descending sequence from ➂ to ➀. Then,

the suspended processing is resumed from where it

left off.

6.1 Overview

The M37905 provides 32 (including the reset) interrupt sources to generate interrupt requests.

Figure 6.1.1 shows the interrupt processing sequence.

When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set

in the interrupt vector table (addresses FFB416 to FFFF16). Set the start address of each interrupt routine to

the corresponding interrupt vector address in the interrupt vector table.

6.1 Overview

Fig. 6.1.1 Interrupt processing sequence

Interrupt routine

Interrupt request is accepted.

Processing is resumed.

Processing is suspended.

Returns

to original

routine.

RTI instruction

Interrupt processing

Routine in progress

Branches

to start

address

of interrupt

routine.

[S] is an initial address that the stack pointer (S) indicates

when an interrupt request is accepted. The S’s contents

become “[S] – 5” after all of the above registers are pushed.

Address

[S] – 4

[S] – 3

[S] – 2

[S] – 1

[S]✽

Processor status register’s low-order byte (PSL)

Stack area

[S] – 5

Processor status register’s high-order byte (PSH)

Program counter’s low-order byte (PCL)

Program counter’s high-order byte (PCH)

Program bank register (PG)

✽

Fig. 6.1.2 State of stack area just before entering

interrupt routine

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