MAX11008 datasheet(21/67 Pages) MAXIM

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Slave Address

A bus master initiates communication with a slave

device by issuing a START condition followed by the 7-

bit slave address and a read/

write (R/W) bit (see Figure

7). When the device recognizes its slave address, it is

ready to accept or send data depending on the R/

bit. When the MAX11008 recognizes its slave address,

it issues an ACK by pulling SDA low for one clock cycle

and is ready to accept or send data depending on the

W bit that was sent.

The MAX11008 has eight user-selectable slave address-

es, which are set through inputs A0, A1, and A2 (see

Table 1). This feature allows up to eight MAX11008

devices to share the same bus inputs. The 4 MSBs D[7:4]

are factory set, and the 3 LSBs are user-selectable.

Bus Timing

At power-up, the bus timing is set for I2C fast-mode

(F/S mode), which allows I2C clock rates up to 400kHz.

The MAX11008 can also operate in high-speed mode

(HS mode) to achieve I2C clock rates up to 3.4MHz.

See Figure 4 for I2C bus timing.

HS I2C Mode

Select HS mode by addressing all devices on the bus

with the HS-mode master code 0000 1XXX (X = don’t

care). After successfully receiving the HS-mode master

code, the MAX11008 issues a NACK, allowing SDA to

be pulled high for one clock cycle (see Figure 8). After

the NACK, the MAX11008 operates in HS mode. The

master must then send a repeated START (Sr) followed

by a slave address to initiate HS-mode communication.

If the master generates a STOP condition, the

Dual RF LDMOS Bias Controller with

Nonvolatile Memory

______________________________________________________________________________________

SDA

SCL

R/W

Figure 7. Slave Address Bits

SDA

HS MODE

F/S MODE

Figure 8. F/S-Mode to HS-Mode Transfer

ADDRESS

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

Table 1. Slave Address Select

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