PCF2123 datasheet(12/54 Pages) NXP

12 / 54 page

PCF2123_1

Product data sheet

Rev. 01 — 19 November 2008

12 of 54

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI

or OSCO. The oscillator is also considered to be stopped during the time between

power-on and stable crystal resonance. This time may be in the range of 200 ms to 2 s

depending on crystal type, temperature and supply voltage. At power-on the OS ﬂag is

always set.

9.5 Reset

A reset is automatically generated at power-on. A reset can also be initiated with the

software reset command. It is generally recommended to make a software reset after

power-on.

A software reset can be initiated by setting the bits 6, 4 and 3 in register Control_1 to

logic 1 and all other bits to logic 0 by sending the bit sequence 01011000 (58h), see

Figure 10. If this bit sequence is not correct, the software reset instruction will be ignored

to protect the device from accidently being reset. When sending the software instruction,

the other bits are not written.

The SPI-bus is reset whenever the chip enable pin CE is inactive.

Fig 9.

OS ﬂag

001aai553

OS = 1 and flag can not be cleared

OS = 1 and flag can be cleared

OS flag cleared

by software

OS flag set when

oscillation stops

oscillation now stable

VDD

oscillation

OS flag

(1) When CE is inactive, the interface is reset.

Fig 10. Software reset command

001aai562

addr 00HEX

software reset 58HEX

R/W

internal

reset signal

SCL

(1)

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