PCK953_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 9 October 2008

3 of 15

NXP Semiconductors

PCK953

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver

5.2 Pin description

6.

Functional description

Refer to Figure 1 “Functional diagram”.

6.1 Function selection

Table 2.

Pin description

Symbol

Pin

Description

1

Analog supply voltage. See Section 11 “Application information” for

design and layout considerations.

FB_CLK

2

Feedback clock input (CMOS) to comparator/phase detector.

n.c.

3, 4, 5, 6

Not connected.

GNDI

7

Ground pin associated with input circuitry.

PECL_CLK

8

LVPECL reference clock input, true.

PECL_CLK

9

LVPECL reference clock input, complementary.

MR/OE

10

Master reset/output enable input. See Table 3 “Function selection”.

11, 15, 19,

23, 27

Supply voltage pins associated with output driver circuitry.

Q7

12

Buffered clock outputs (CMOS).

Q6

14

Q5

16

Q4

18

Q3

20

Q2

22

Q1

24

Q0

26

GNDO

13, 17, 21,

25, 29

Ground pins associated with output driver circuitry.

QFB

28

Buffered clock output intended to be fed to feedback pin FB_CLK.

PLL_EN

30

PLL enable input pin. See Table 3 “Function selection”.

BYPASS

31

Bypass input pin. See Table 3 “Function selection”.

VCO_SEL

32

VCO select input pin. See Table 3 “Function selection”.

Table 3.

Function selection

Pin

Value

Function

BYPASS

1

PLL enabled

0

PLL bypass

MR/OE

1

outputs disabled

0

outputs enabled

VCO_SEL

1

divide-by-2

0

divide-by-1

PLL_EN

1

select VCO

0

select PECL_CLK