1.

General description

The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high

performance clock tree designs. With output frequencies of up to 125 MHz, and output

skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The

devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.

The PCK953 has a differential LVPECL reference input, along with an external feedback

input. These features make the PCK953 ideal for use as a zero delay, low skew fan-out

buffer. The device performance has been tuned and optimized for zero delay performance.

The MR/OE input pin will reset the internal counters and 3-state the output buffers when

driven HIGH.

The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All

control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide

LVCMOS levels with the ability to drive terminated 50

Ω transmission lines. For series

terminated 50

Ω lines, each of the PCK953 outputs can drive two traces, giving the device

an effective fan-out of 1 : 18. The device is packaged in a 7 mm

× 7 mm 32-lead LQFP

package to provide the optimum combination of board density and performance.

2.

Features

PCK953

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

clock driver

Rev. 05 — 9 October 2008

Product data sheet