PCK953_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 9 October 2008

5 of 15

NXP Semiconductors

PCK953

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver

9.

Dynamic characteristics

10. PLL input reference characteristics

Table 6.

Dynamic characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

output rise time

0.8 V to 2.0 V

0.30

0.55

0.8

ns

output fall time

0.8 V to 2.0 V

0.30

0.55

0.8

ns

output duty cycle

45

50

55

%

output skew time

output-to-output; relative to QFB

-

-

100

ps

PLL VCO lock range

120

-

500

MHz

maximum output frequency

PLL mode; VCO_SEL = 1

20

-

100

MHz

PLL mode; VCO_SEL = 0

35

-

125

MHz

Bypass mode

-

-

225

MHz

input to EXT_FB delay (with

PLL locked)

−75

-

+125

ps

input to Qn delay

PLL bypassed

3

5.2

7

ns

output disable time

-

-

7

ns

output enable time

-

-

6

ns

cycle-to-cycle jitter time

peak-to-peak

-

55

100

ps

maximum PLL lock time

-

0.01

10

ms

Table 7.

PLL input reference characteristics

Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

reference input frequency

20

-

125

MHz

reference input duty cycle

25

-

75

%