PCK953_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 9 October 2008

8 of 15

NXP Semiconductors

PCK953

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver

(2)

At the load end, the voltage will double due to the near unity reflection coefficient, to

2.62 V. It will then increment towards the quiescent 3.0 V in steps separated by one

round-trip delay (in this case, 4.0 ns).

Since this step is well above the threshold region, it will not cause any false clock

triggering, however, designers may be uncomfortable with unwanted reflections on the

line. To better match the impedances when driving multiple lines, the situation in Figure 6

should be used. In this case, the series terminating resistors are reduced such that when

the parallel combination is added to the output buffer impedance, the line impedance is

perfectly matched.

SPICE level output buffer models are available for engineers who want to simulate their

specific interconnect schemes. In addition, IV characteristics are in the process of being

generated to support the other board-level simulators in general use.

Fig 5.

Single versus dual waveforms

14

Ω +22 Ω|| 22 Ω =50 Ω|| 50 Ω

25

Ω =25 Ω

Fig 6.

Optimized dual line termination

V

L

3.0

25

18

14

25

++

------------------------------





3.0

25

57

------





1.31 V

==

=

time (ns)

016

12

48

002aae141

3.0

voltage

(V)

−0.5

0

1.0

2.0

IN

OutA

OutB

Zo = 50 Ω

002aae142

Rs = 22 Ω

Zo = 50 Ω

Rs = 22 Ω

PCK953

OUTPUT BUFFER

14

Ω

IN

Ro