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TDF8599 Datasheet(PDF) 22 Page - NXP Semiconductors |
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TDF8599 Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 52 page ![]() TDF8599_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 22 of 52 NXP Semiconductors TDF8599 Class-D power amplifier with load diagnostics In Parallel mode, disabling clip detection on both channels requires both bits to be set to bit IB1[D5] = 1 and bit IB2[D5] = 1. 8.6.3 Start-up and shutdown sequence To prevent the switch on or switch off ‘pop noise’, a capacitor (CSVR) connected to pin SVR is used to smooth start-up and shutdown. During start-up and shutdown, the output voltage tracks the voltage on pin SVR. Increasing CSVR results in a longer start-up and shutdown time. Enhanced pop performance is achieved by muting the amplifier until the SVR voltage reaches its final value and the outputs start switching. The capacitor on the pin SEL_MUTE (CON) determines the unmute and mute timing. The voltage on pin SEL_MUTE determines the amplifier gain. Increasing CON increases the unmute and mute times. In addition, a larger CON value increases the DC load detection cycle. When the amplifier is switched off with an I2C-bus command or by pulling pin EN low, the amplifier is first muted and then capacitor (CSVR) is discharged. In Slave mode, the device enters the off state immediately after capacitor (CSVR) is discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of approximately 50 ms to allow slave devices to enter off state. When an external clock is connected to pin OSCIO (in Slave mode), the clock remains active during the shutdown sequence (td(1)) to ensure that the slaved TDF8599 devices are able to enter the off state. (1) Shutdown hold delay (2) Master mode shutdown delay (3) Shutdown delay Fig 21. Start-up and shutdown timing in I2C-bus mode with DC load detection 001aai790 VDDA DIAG EN ACGND IB1[D0] and IB2[D0]=0 SEL_MUTE SVR OUT td(2) td(1) mute on delay td(stb-mute) twake tdet(DCload) td(3) |
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