TDF8599 datasheet(30/52 Pages) NXP

30 / 52 page

TDF8599_1

Product data sheet

Rev. 01 — 13 November 2008

30 of 52

NXP Semiconductors

TDF8599

Class-D power ampliﬁer with load diagnostics

[1]

Required resistor accuracy for pins ADS and MOD is 1 %; see Section 9 on page 23.

[2]

Maximum leakage current from DCP pin to ground = 3

µA.

[3]

DC output offset voltage is applied to the output during the transition between Mute mode and Operating mode in a gradual way.

[4]

I2C-bus mode only.

[5]

The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin.

[6]

The DC load valid bit DB1[D6] must be used; Section 8.6.2.1 on page 19. The DC load enable bit IB2[D2] must be reset after each load

detection cycle to prevent ampliﬁer hang-up incidents.

delay time

shutdown delay time from EN pin

low to SVRR low; SVRR < 0.1 V;

CSVR =47 µF

145

260

425

shutdown delay time from pin EN

low to ACGND low; voltage on pin

ACGND < 0.1 V; Master mode

400

delay in Master mode to allow

slaved devices to shutdown

fosc = 320 kHz

-50

Speaker load impedance

load resistance

stereo mode

1.6

Ω

parallel mode

0.8

Ω

Table 19.

Static characteristics …continued

Vp = 14.4 V; fosc = 320 kHz; −40 °C < Tamb < +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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