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LTC4265 Datasheet(PDF) 9 Page - Linear Technology

Part # LTC4265
Description  IEEE 802.3at High Power PD Interface Controller with 2-Event Classifi cation Recognition
PDF  20 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4265 Datasheet(HTML) 9 Page - Linear Technology

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LTC4265
9
4265f
APPLICATIONS INFORMATION
In 2-event classification, a Type-2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 14.5V to
20.5V and the LTC4265 presents a class 4 load current.
The PSE then drops the input voltage into the mark volt-
age range of 6.9V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
The PSE repeats this sequence, signaling the 2nd Clas-
sification and 2nd mark event occurrence. This alerts the
LTC4265 that a Type-2 PSE is present. The Type-2 PSE
then applies power to the PD and the LTC4265 charges
up the reservoir capacitor C1 with a controlled inrush cur-
rent. When C1 is fully charged, and the LTC4265 declares
power good, the T2PSE pin presents an active low signal,
or low impedance output with respect to VIN. The T2PSE
output becomes inactive when the LTC4265 input voltage
falls outside the normal operating range.
SIGNATURE CORRUPT DURING MARK
As a member of the IEEE802.3at working group, Linear
notes that it is possible for a Type-2 PD to receive a
false indication of a 2-event classification if a PSE port
is pre-charged to a voltage above the detection voltage
range before the first detection cycle. The IEEE working
group modified the standard to prevent this possibility by
requiring a Type-2 PD to corrupt the signature resistance
during the mark event, alerting the PSE not to apply power.
The LTC4265 conforms to this standard by internally
corrupting the signature resistance. This also discharges
the port before the PSE begins the next detection cycle.
DETECTION V1
ON
UVLO
UVLO
UVLO
ON
= RLOAD C1
TRACKS
VIN
DETECTION V2
TIME
50
40
30
20
10
40mA
50
40
30
20
10
TIME
–10
TIME
–20
–30
–40
–50
dV
dt
INRUSH
C1
=
4265 F04
INRUSH = 100mA
RCLASS = 30.9Ω
ILOAD =
VIN
RLOAD
GND
PSE
IIN
RLOAD
RCLASS
VOUT
C1
GND
RCLASS
T2PSE
LTC4265
VOUT
VIN
1st CLASS
1st MARK 2nd MARK
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
2nd CLASS
1st CLASS
2nd CLASS
LOAD, ILOAD
INRUSH
Figure 4. VOUT, T2PSE, and PD Current
as a Result of 2-event Classification



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