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LTC2483

2483f

Initiating a New Conversion

When the LTC2483 finishes a conversion, it automatically

enters the sleep state. Once in the sleep state, the device

is ready for a Read operation. After the device acknowl-

edges a Read request, the device exits the sleep state and

enters the data output state. The data output state con-

cludes and the LTC2483 starts a new conversion once a

STOP condition is issued by the master or all 24-bits of

data are read out of the device.

During the data read cycle, a stop command may be issued

by the master controller in order to start a new conversion

and abort the data transfer. This stop command must be

issued during the 9th clock cycle of a byte read when the

bus is free (the ACK/NAK cycle).

LTC2483 Address

The LTC2483 has two address pins, enabling one in 6

possible addresses, as shown in Table 3.

Table 3. LTC2483 Address Assignment

CA1

CA0/F0 *

Address

LOW

HIGH

001 01 00

LOW

Floating

001 01 01

Floating

HIGH

001 01 11

Floating

010 01 00

HIGH

010 01 10

HIGH

Floating

010 01 11

* CA0/F0 is treated as HIGH when driven by a valid external clock.

Data Read

The data read operation sequence is shown in Figure 5.

When the conversion is finished, the device may be

addressed for a read operation. At the end of a read

operation, a new conversion begins. At the conclusion

of the conversion cycle, the next result may be read

using the method described above. If the conversion

cycle is not concluded and a valid address selects the

device, the LTC2483 generates a NAK signal indicating

the conversion cycle is in progress.

Easy Drive Input Current Cancellation

The LTC2483 combines a high precision delta-sigma ADC

with an automatic differential input current cancellation

front end. A proprietary front-end passive sampling

network transparently removes the differential input cur-

rent. This enables external RC networks and high imped-

ance sensors to directly interface to the LTC2483 without

external amplifiers. The remaining common mode input

current is eliminated by either balancing the differential

input impedances or setting the common mode input

equal to the common mode reference (see Automatic

Input Current Cancellation section). This unique architec-

ture does not require on-chip buffers enabling input

signals to swing all the way to ground and up to VCC.

Furthermore, the cancellation does not interfere with the

transparent offset and full-scale auto-calibration and the

absolute accuracy (full scale + offset + linearity) is main-

tained even with external RC networks.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a SINC or Comb filter). For high

resolution, low frequency applications, this filter is typically

designed to reject line frequencies of 50Hz and 60Hz plus

their harmonics. The filter rejection performance is directly

related to the accuracy of the converter system clock. The

LTC2483 incorporates a highly accurate on-chip oscillator.

This eliminates the need for external frequency setting com-

ponents such as crystals or oscillators.

APPLICATIO S I FOR ATIO

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