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LTC2483

2483f

normal mode rejection in a frequency range of fEOSC/5120

±4% and its harmonics. The normal mode rejection as a

function of the input frequency deviation from fEOSC/5120

is shown in Figure 6.

Ease of Use

The LTC2483 data output has no latency, filter settling

delay or redundant data associated with the conversion

cycle. There is a one-to-one correspondence between the

conversion and the output data. Therefore, multiplexing

multiple analog voltages is easy.

The LTC2483 performs offset and full-scale calibrations

every conversion cycle. This calibration is transparent to the

user and has no effect on the cyclic operation described

above. The advantage of continuous calibration is extreme

stability of offset and full-scale readings with respect to

time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2483 automatically enters an internal reset state

when the power supply voltage VCC drops below approxi-

mately 2V. This feature guarantees the integrity of the conver-

sion result.

When the VCC voltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signal with a duration of approximately 4ms. The POR

signal clears all internal registers. Following the POR

signal, the LTC2483 starts a normal conversion cycle and

follows the succession of states described in Figure 1. The

first conversion result following POR is accurate within the

specifications of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

Reference Voltage Range

The LTC2483 external reference voltage range is 0.1V to

VCC. The converter output noise is determined by the

APPLICATIO S I FOR ATIO

Figure 6. LTC2483 Normal Mode Rejection When

Using an External Oscillator

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)

–12

–8

–4

2483 F06

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

Whenever an external clock is not present at the CA0/F0

pin, the converter automatically activates its internal os-

cillator and enters the Internal Conversion Clock mode.

CA0/F0 may be tied HIGH or left floating in order to set the

chip address. The LTC2483 operation will not be dis-

turbed if the change of conversion clock source occurs

during the sleep state or during the data output state while

the converter uses an external serial clock. If the change

occurs during the conversion state, the result of the

conversion in progress may be outside specifications but

the following conversions will not be affected.

Table 4 summarizes the duration of the conversion state of

each state and the achievable output data rate as a function

of fEOSC.

Table 4. LTC2483 State Duration

STATE

OPERATING MODE

DURATION

CONVERSION

Internal Oscillator

50Hz/60Hz Rejection

147ms, Output Data Rate

≤ 6.8 Readings/s

External Oscillator

CA0/F0 = External Oscillator with Frequency 41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s

fEOSC Hz (fEOSC/5120 Rejection)

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