LTC3219 datasheet(6/20 Pages) LINER

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LTC3219

3219fa

PIN FUNCTIONS

CPO (Pin 1): Output of the Charge Pump Used to Power

all LEDs. A 2.2μF X5R or X7R ceramic capacitor should

be connected to ground.

ULED1-ULED9 (Pins 2 to 6, Pins 11 to 14): Current Source

Outputs for Driving LEDs. The LED current can be set from

0mA to 28mA in 64 steps via software control and internal

6-bit linear DAC. Each output can be disabled by setting the

associated data register REG1-REG9 to 0. ULED1-ULED9

can also be used as I2C controlled open-drain outputs.

Connect unused outputs to ground.

DVCC (Pin 7): Supply Voltage for All Digital I/O Lines. This

pin sets the logic reference level of the LTC3219. DVCC will

reset the data registers when set below the undervoltage

lockout threshold, which is the recommended method

for resetting the part after power-up. A 0.1μF X5R or X7R

ceramic capacitor should be connected to ground.

SCL (Pin 8): I2C Clock Input. The logic level for SCL is

referenced to DVCC.

SDA (Pin 9): Input Data for the Serial Port. Serial data is

shifted in one bit per clock to control the LTC3219. The

logic level is referenced to DVCC.

ENU (Pin 10): Input. Used to enable or disable the pre-

selected ULED outputs. When the pin is toggled from

low (disable) to high (enable), the LTC3219 illuminates

the pre-selected LEDs. When ENU is controlling selected

outputs and other outputs have been enabled, the charge

pump mode will be reset to 1x on the falling edge of ENU.

When ENU is controlling selected outputs and no other

outputs are active, the part will go from enabled to shut-

down. The ENU logic level is referenced to DVCC. This pin

is connected to ground if unused.

GND (Pin 15, 21): System Ground. Connect Pin 15 and

the Exposed Pad (Pin 21) to the ground plane.

C1P, C2P, C1M, C2M (Pins 20, 19, 17, 16): Charge Pump

Flying Capacitor Pins. A 1μF X7R or X5R ceramic capaci-

tor should be connected from C1P to C1M and C2P to

C2M.

VBAT (Pin 18): Supply Voltage for the Entire Device. This

pin should be bypassed with a single 2.2μF low ESR

ceramic capacitor.

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