BQ2011 datasheet(11/20 Pages) TI

11 / 20 page

The W/R values are:

Where W/R is:

The bq2011 outputs the requested register

contents specified by the address portion of

CMDR.

The following eight bits should be written

to the register specified by the address por-

tion of CMDR.

The lower seven-bit field of CMDR contains the address

portion of the register to be accessed. Attempts to write

to invalid addresses are ignored.

Primary Status Flags Register (FLGS1)

The read-only FLGS1 register (address=01h) contains

the primary bq2011 flags.

The charge status flag (CHGS) is asserted when a

valid charge rate is detected.

Charge rate is deemed

valid when VSRO < -400

µV. A VSRO of greater than-

400

µV or discharge activity clears CHGS.

The CHGS values are:

Where CHGS is:

Either discharge activity detected or VSRO >

-400

µV

1VSRO < -400

µV

The battery replaced flag (BRP) is asserted whenever

the potential on the SB pin (relative to VSS), VSB, rises

above 0.1V and determines the internal registers have

been corrupted.

The BRP flag is also set when the

bq2011 is reset (see the RST register description). BRP

is latched until either the bq2011 is charged until NAC

= LMD or discharged until EDV is reached. BRP = 1

signifies that the device has been reset.

The BRP values are:

Where BRP is:

bq2011 is charged until NAC = LMD or dis-

charged until the EDV flag is asserted

SB rising from below 0.1V, or a serial port

initiated reset has occurred

The maximum cell voltage flag (MCV)

is asserted

whenever the potential on the SB pin (relative to VSS)is

above 2.0V. The MCV flag is asserted until the condi-

tion causing MCV is removed.

The MCV values are:

Where MCV is:

0VSB < 2.0V

1VSB > 2.0V

The capacity inaccurate flag (CI) is used to warn the

user that the battery has been charged a substantial

number of times since LMD has been updated. The CI

flag is asserted on the 64th charge after the last LMD

update or when the bq2011 is reset. The flag is cleared

after an LMD update.

The CI values are:

Where CI is:

When LMD is updated with a valid full dis-

charge or the bq2011 is reset

After the 64th valid charge action with no

LMD updates

bq2011

FLGS1 Bits

MCV

FLGS1 Bits

CHGS

FLGS1 Bits

BRP

CMDR Bits

AD6 AD5

AD4

AD3

AD2

AD1

AD0

(LSB)

CMDR Bits

W/R

BQ2011 Datasheet(PDF) 11 Page - Texas Instruments

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