BQ2011 datasheet(14/20 Pages) TI

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Full Count Register (FULCNT)

The read-only FULCNT register (address=0bh) provides

the system with a diagnostic of the number of times the

battery has been fully charged (NAC = LMD).

The

number of full occurrences can be determined by multiply-

ing the value in the FULCNT register by 16. Any dis-

charge action other than self-discharge allows detection of

another full occurrence during the next valid charge ac-

tion.

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in-

dicate the number of times a battery has been charged

without an LMD update. Because the capacity of a re-

chargeable battery varies with age and operating condi-

tions, the bq2011 adapts to the changing capacity over

time.

A complete discharge from full (NAC=LMD) to

empty (EDV=1) is required to perform an LMD update

assuming there have been no intervening valid charges,

the temperature is greater than or equal to 0°C, and the

self-discharge counter is less than 4096 counts.

The CPI register is incremented every time a valid

charge is detected. The register increments to 255 with-

out rolling over. When the contents of CPI are incre-

mented to 64, the capacity inaccurate flag, CI, is as-

serted in the FLGS1 register. CPI is reset whenever an

update of the LMD register is performed, and the CI flag

is also cleared.

Output Control Register (OCTL)

The write-only OCTL register (address=0ah) provides

the system with a means to check the display connec-

tions for the bq2011. The segment drivers may be over-

written by data from OCTL when the least-significant

bit of OCTL, OCE, is set. The data in bits OC5–1 of the

OCTL register (see Table 4 on page 10 for details) is out-

put onto the segment pins, SEG5–1, respectively if

OCE=1.

Whenever OCE is written to 1, the MSB of

OCTL should be set to a 1. The OCE register location

must be cleared to return the bq2011 to normal opera-

tion. OCE may be cleared by either writing the bit to a

logic zero via the serial port or by resetting the bq2011

as explained below. Note: Whenever the OCTL register is

written, the MSB of OCTL should be written to a logic one.

Reset Register (RST)

The reset register (address=39h) provides the means to

perform a software-controlled reset of the device. A full

device reset may be accomplished by first writing LMD

(address = 05h) to 00h and then writing the RST regis-

ter contents from 00h to 80h. Setting any bit other than

the most-significant bit of the RST register is not al-

lowed, and results in improper operation of the bq2011.

Resetting the bq2011 sets the following:

LMD = PFC

CPI, VDQ, NAC, and OCE = 0 or

NAC = LMD when SEG5 = L

CI and BRP = 1

Display

The bq2011 can directly display capacity information

using low-power LEDs. If LEDs are used, the segment

pins should be tied to VCC, the battery, or the MODE pin

for programming the bq2011.

The bq2011 displays the battery charge state in either

absolute or relative mode. In relative mode, the battery

charge is represented as a percentage of the LMD. Each

LED segment represents 20% of the LMD.

In absolute mode, each segment represents a fixed

amount of charge, based on the initial PFC. In absolute

mode, each segment represents 20% of the PFC. As the

battery wears out over time, it is possible for the LMD

to be below the initial PFC. In this case, all of the LEDs

may not turn on, representing the reduction in the ac-

tual battery capacity.

The capacity display is also adjusted for the present bat-

tery temperature. The temperature adjustment reflects

the available capacity at a given temperature but does

not affect the NAC register. The temperature adjust-

ments are detailed in the TMPGG register description.

When DISP is tied to VCC, the SEG1–5 outputs are inac-

tive. When DISP is left floating, the display becomes ac-

tive during charge if the NAC registers are counting at a

rate equivalent to VSRO < -1mV or fast discharge if the

NAC registers are counting at a rate equivalent to VSRO

> 2mV. When pulled low, the segment output becomes

active for 4 seconds,

±0.5 seconds.

The segment outputs are modulated as two banks, with

segments 1, 3, and 5 alternating with segments 2 and 4.

The segment outputs are modulated at approximately

320Hz, with each bank active for 30% of the period.

SEG1 blinks at a 4Hz rate whenever VSB has been de-

tected to be below VEDV to indicate a low-battery condi-

tion or NAC is less than 10% of the LMD or PFC, de-

pending on the display mode.

Microregulator

The bq2011 can operate directly from 4 cells. To facilitate

the power supply requirements of the bq2011, an REF out-

put is provided to regulate an external low-threshold n-

FET. A micropower source for the bq2011 can be inexpen-

sively built using the FET and an external resistor.

bq2011

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