PCI1420 datasheet(39/137 Pages) TI

39 / 137 page

3–9

Two socket function dependent PCI configuration header registers that are critical for DDMA are the socket DMA

socket DMA register 0 and the contents of this register configure the PC Card-16 terminal (SPKR, IOIS16, or INPACK)

which is used for the DMA request signal, DREQ. The base address of the DDMA slave registers and the transfer

size (bytes or words) are programmed through the socket DMA register 1. Refer to the programming model and

Table 3–3. Distributed DMA Registers

TYPE

DMA

BASE ADDRESS

OFFSET

Reserved

Page

Current address

00h

Reserved

Page

Base address

Reserved

Current count

04h

Reserved

Base count

N/A

Reserved

N/A

Status

08h

Mode

Reserved

Request

Command

Multichannel

Reserved

N/A

Reserved

0Ch

Mask

Reserved

Master clear

Reserved

The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the

those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA controller do not

apply to distributed DMA in a PCI environment. In such cases, the PCI1420 implements these obsolete register bits

as read-only, nonfunctional bits. The reserved registers shown in Table 3–3 are implemented as read-only and return

0s when read. Write transactions to reserved registers have no effect.

The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed

after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal assignment,

setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done

through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an

8237 controller, and the PCI1420 awaits a DREQ assertion from the PC Card requesting a DMA transfer.

DMA writes transfer data from the PC Card-to-PCI memory addresses. The PCI1420 accepts data 8 or 16 bits at a

time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ signal.

Once the PCI bus is granted in an idle state, the PCI1420 initiates a PCI memory write command to the current

memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1420 accepts

the next byte(s) from the PC Card until the transfer count expires.

DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ, the

PCI1420 asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1420 initiates a PCI

memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the

programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After terminating the

PC Card cycle, the PCI1420 requests access to the PCI bus again until the transfer count has expired.

The PCI1420 target interface acts normally during this procedure and accepts I/O reads and writes to the DDMA

registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1420 asserts TC and

ends the PC Card cycle(s). TC is indicated in the DMA status register (see Section 7.5). At the PC Card interface,

the PCI1420 supports demand mode transfers. The PCI1420 asserts DACK during the transfer unless DREQ is

deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to WE

PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all transfers,

and the DREQ terminal is routed to one of three options which is programmed through socket DMA register 0.

PCI1420 Datasheet(PDF) 39 Page - Texas Instruments

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