PCI1420 datasheet(77/137 Pages) TI

77 / 137 page

4–21

4.31 Retry Status Register

The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set

when the PCI1420 retries a PCI or CardBus master request and the master does not return within 215 PCI clock

cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI

command, PCI status, and bridge control registers by the PCI SIG. Access this register only through function 0. See

Table 4–9 for a complete description of the register contents.

Bit

Name

Retry status

Type

R/W

R/C

Default

Retry status

Type:

Read-only, Read/Write, Read/Write to Clear

Offset:

90h (functions 0, 1)

Default:

C0h

Table 4–9. Retry Status Register

BIT

SIGNAL

TYPE

FUNCTION

PCIRETRY

R/W

PCI retry timeout counter enable. Bit 7 is encoded:

0 = PCI retry counter disabled

1 = PCI retry counter enabled (default)

6†

CBRETRY

R/W

CardBus retry timeout counter enable. Bit 6 is encoded:

0 = CardBus retry counter disabled

1 = CardBus retry counter enabled (default)

TEXP_CBB

R/C

CardBus target B retry expired. Write a 1 to clear bit 5.

0 = Inactive (default)

1 = Retry has expired

RSVD

Reserved. Bit 4 returns 0 when read.

3†

TEXP_CBA

R/C

CardBus target A retry expired. Write a 1 to clear bit 3.

0 = Inactive (default)

1 = Retry has expired.

RSVD

Reserved. Bit 2 returns 0 when read.

TEXP_PCI

R/C

PCI target retry expired. Write a 1 to clear bit 1.

0 = Inactive (default)

1 = Retry has expired.

RSVD

Reserved. Bit 0 returns 0 when read.

† This bit is global and is accessed only through function 0.

PCI1420 Datasheet(PDF) 77 Page - Texas Instruments

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