PCI1420 datasheet(93/137 Pages) TI

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5–1

5 ExCA Compatibility Registers (Functions 0 and 1)

The ExCA registers implemented in the PCI1420 are register-compatible with the Intel 82365SL–DF PCMCIA

controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme

used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register

offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base

address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base address register

(see Section 4.28), which is shared by both card sockets. The offsets from this base address run contiguous from

00h to 3Fh for socket A, and from 40h to 7Fh for socket B. See Figure 5–1 for an ExCA I/O mapping illustration.

CardBus Socket/ExCA Base Address

16-Bit Legacy-Mode Base Address

10h

44h

00h

3Fh

Offset

Index

Host I/O Space

Data

PC Card A

ExCA

Registers

PC Card B

ExCA

Registers

40h

7Fh

NOTE: The 16-bit legacy mode base address register is shared by functions 0 and 1 as indicated by the shading.

PCI1420 Configuration Registers

Offset

Figure 5–1. ExCA Register Access Through I/O

The TI PCI1420 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI

memory space. They are located through the CardBus socket registers/ExCA base address register (see

Section 4.12) at memory offset 800h. Each socket has a separate base address programmable by function. See

Figure 5–2 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both functions

0 and 1. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K

window at memory offset 0h.

PCI1420 Datasheet(PDF) 93 Page - Texas Instruments