PCI1420 datasheet(43/137 Pages) TI

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3–13

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

S/P = Start/stop condition

A = Slave acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Figure 3–12. Serial Bus Protocol – Byte Write

Figure 3–13 illustrates a byte read. The read protocol is very similar to the write protocol except the R/W command

bit must be set to 1 to indicate a read-data transfer. In addition, the PCI1420 master must acknowledge reception

of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers.

The SCL signal remains driven by the PCI1420 master.

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

S/P = Start/stop condition

A = Slave acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Figure 3–13. Serial Bus Protocol – Byte Read

Figure 3–14 illustrates EEPROM interface doubleword data collection protocol.

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

Data Byte 2

Data Byte 1

Data Byte 0

M = Master acknowledgement

S/P = Start/stop condition

A = Slave acknowledgement

Data Byte 3

001

Restart

R/W

Slave Address

Start

Figure 3–14. EEPROM Interface Doubleword Data Collection

3.6.3

Serial Bus EEPROM Application

When the PCI bus is reset and the serial bus interface is detected, the PCI1420 attempts to read the subsystem

identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be

loaded with defaults through the EEPROM are provided in Table 3–7.

Table 3–7. Registers and Bits Loadable Through Serial EEPROM

OFFSET

REFERENCE

PCI OFFSET

BITS LOADED FROM EEPROM

01h

40h

Subsystem ID

31–0

02h

80h

System control

31–29, 27, 26, 24, 15, 14, 6–3, 1

03h

8Ch

Multifunction routing

27–0

04h

90h

Retry status, card control, device control, diagnostic

31, 28–24, 22, 19–16, 15, 13, 7, 6

Figure 3–15 details the EEPROM data format. This format must be followed for the PCI1420 to properly load

initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the ROM_ERR

bit in the serial bus control and status register (see Section 4.50).

PCI1420 Datasheet(PDF) 43 Page - Texas Instruments

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