PCI4450 datasheet(43/197 Pages) TI

43 / 197 page

PCI4450 GFN/GJG

PC Card and OHCI Controller

SCPS046 – JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

The RI signal from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the ExCA interrupt

and general control register. This is programmed on a per socket basis, and is only applicable when a 16-bit

card is powered in the socket.

The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The

mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers.

PC CARD CONTROLLER PROGRAMMING MODEL

This section describes the PCI4450 PCI configuration registers that make up the 256-byte PCI configuration

header for each PCI4450 function. As noted below, some bits are global in nature and should be accessed only

through function 0.

Registers containing one or more global bits are denoted by a “§.”

Any bit followed by a “†” is not cleared by the assertion of PRST (refer to

CardBus device class power

management for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are only cleared

by G_RST. If PME is not enabled, then these bits are cleared by G_RST or PRST. These bits are sometimes

referred to as PME context bits and are implemented to allow PME context to be preserved when transitioning

from D3hot or D3cold to D0. If the PME context PRST functionality is not desired, then the PRST and G_RST

signals should be tied together.

If a bit is followed by a “‡”, then this bit is only cleared by G_RST in all cases (not conditional on PME being

enabled). These bits are intended to maintain device context such as interrupt routing and MFUNC

programming during “warm” resets.

PCI configuration registers (functions 0 and 1)

The PCI4450 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1.

The configuration header, compliant with the PCI Specification as a CardBus bridge header, is PC97/PC98

compliant as well. Table 24 illustrates the PCI configuration header, which includes both the predefined portion

of the configuration space and the user definable registers.

PCI4450 Datasheet(PDF) 43 Page - Texas Instruments